Final Program
| Wednesday, 8 December 2010 |
| 0900-1230 | Short Course 1 (SC1) | Short Course 2 (SC2) | Short Course 5 (SC5) |
|
Package and Board Level Reliability Part 1-Accelerated Testing and Design for Reliability by Ahmer SYED, Amkor |
Flip Chip Fabrication and Interconnection
by Eric PERFECTO, IBM |
Electrical Test Strategies for High-Density Package
by Bruce C. KIM, The University of Alabama |
|
| 1230-1330 | Lunch | ||
| 1330-1700 | Short Course 3 (SC3) | Short Course 4 (SC4) | Short Course 6 (SC6) |
|
Package and Board Level Reliability Part 2-Finite Element Simulations for Failure Prediction by Ahmer SYED, Amkor |
3D IC/Si Integrations and WLP
by John H. LAU, ITRI |
Advanced Failure Analysis of Semiconductor Packaging
by Siegfried GOERLICH and Ming XUE, Infineon |
|
| Thursday, 9 December 2010 |
| 0830-0900 | Registration | ||||
|
0900 - 0915 |
Welcome Address Opening Address |
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|
0915 - 1000 |
Keynote Address 1 Next Generation Packages for Mobile Products: Dawn of a New Age or Same Old Story? by Mr. Tom Gregorich, MediaTek, USA |
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|
1000 - 1045 |
Keynote Address 2 Digital µ-Fabrication Methods based on Printing Technologies by Prof. Reinhard R. Baumann, Fraunhofer Institute, Germany |
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| 1045-1130 | Tea and Coffee Break | ||||
| 1045-1720 | Table Top Exhibition and Poster Session | ||||
|
1130 - 1230 |
Technical Sessions - A | ||||
| White Gardenia Room | Red Gardenia Room | Green Orchid Room | Yellow Orchid Room | Hibiscus Room | |
|
A1 Emerging Technology I |
A2 Wafer Process |
A3 Wirebonding I |
A4 Material & Process I |
A5 Thermal Design I |
|
| 1230-1400 | Lunch | ||||
|
1400 - 1540 |
Technical Sessions - B | ||||
| White Gardenia Room | Red Gardenia Room | Green Orchid Room | Yellow Orchid Room | Hibiscus Room | |
|
B1 Emerging Technology II |
B2 Electrical Design & Characterization |
B3 Interconnect Technology I |
B4 Material & Process II |
B5 Mechanical Modeling I |
|
| 1540-1620 | Tea and Coffee Break | ||||
|
1620 - 1720 |
Technical Sessions - C | ||||
| White Gardenia Room | Red Gardenia Room | Green Orchid Room | Yellow Orchid Room | Hibiscus Room | |
|
C1 Package Reliability I |
C2 Printed Electronics |
C3 Interconnect Technology II |
C4 Material & Process III |
C5 Thermal Design II |
|
|
1900 - 2200 |
Conference Banquet | ||||
| Friday, 10 December 2010 |
|
0830 - 1010 |
Technical Sessions - D | ||||
| White Gardenia Room | Red Gardenia Room | Green Orchid Room | Yellow Orchid Room | Hibiscus Room | |
|
D1 Interconnect Reliability I |
D2 TSV & Package Reliability |
D3 Wirebonding II |
D4 Material & Process IV |
D5 Packaging Electrical Testing |
|
| 1010-1050 | Tea and Coffee Break | ||||
|
1050 - 1230 |
Technical Sessions - E | ||||
| White Gardenia Room | Red Gardenia Room | Green Orchid Room | Yellow Orchid Room | Hibiscus Room |
E1 Interconnect Reliability II |
E2 Failure Analaysis |
E3 Wirebonding III |
E4 Material & Process V |
E5 Embedded Packaging |
| 1230-1400 | Lunch | ||||
|
1400 - 1530 |
Technical Sessions - F | ||||
| White Gardenia Room | Red Gardenia Room | Green Orchid Room | Yellow Orchid Room | Hibiscus Room | |
|
F1 Interconnect Reliability III |
F2 TSV & Si Integeration |
F3 Wirebonding IV |
F4 Thermal Design III |
F5 Mechanical Modeling II |
|
| 1530-1610 | Tea and Coffee Break + CPMT Workshop | ||||
|
1610 - 1730 |
Technical Sessions - G | ||||
| White Gardenia Room | Red Gardenia Room | Green Orchid Room | Yellow Orchid Room | Hibiscus Room |
G1 Package Reliability II |
G2 Integrated Passives |
G3 Adhesive & Underfill |
G4 Material & Process VI |
G5 Mechanical Modeling III |
